Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include portable computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code, system data such as a basic input/output system (BIOS), and other firmware can typically be stored in flash memory devices. Most electronic devices are designed with a single flash memory device.
In order to increase the memory density of flash memories while making them smaller, the silicon is scaled. Associated with minimum length scaling is a reduction of the oxide thickness and the junctions become less graded. This results in a decrease of the maximum voltage that is tolerated between terminals of the transistors. For example, a high drain-to-source voltage (Vds) could exceed the breakdown limit of the transistor, eventually causing the transistor to fail.
An additional problem is experienced when the gate-to-source voltage (Vgs) goes high while Vds has a high value. This condition is referred to in the art as snapback. The high level of current associated with this phenomenon may damage the device and/or decrease its life.
Flash memory devices require a large negative voltage to erase the memory cells. The negative voltage is generated and regulated by an internal high voltage pump connected to control circuitry to control output of the high voltage.
FIG. 1 illustrates a block diagram of a typical prior art circuit for generating a high negative erase voltage. This circuit is connected to the wordlines of the memory array that are modeled here by a capacitor 101. REFN and REFH are analog values that are used to assign the target voltage values to VNEG and VHV rails, respectively. SELECT passes the high voltages to the sector/sectors that are to be erased. ENABLE activates the erase pulse.
The prior art system can have four different phases that are selected by the ENABLE signal and the VNEG and VHV values. These phases are an off state, ramp phase, pulse phase, and discharge phase.
The off state occurs when ENABLE=0, VNEG and VHV are shorted to ground by the discharge paths 103 and 104. The ramp phase is selected when ENABLE=1, VNEG and VHV are below their target values. The negative and HV pumps 107 and 108 are turned on during this phase. The pulse phase is selected when ENABLE=1, VNEG and VHV are at their target voltages. The negative and HV pumps 107 and 108 are turned off during this phase. The discharge phase is selected when ENABLE=0, VNEG and VHV are discharged to ground; each through its own path 104 and 103 respectively.
The circuit illustrated in FIG. 1 may cause snapback problems that increase the stress some transistors experience during their off state. This decreases the reliability of the transistors in the memory device. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a high voltage management circuit to improve the reliability of memory device transistors.